This application claims the priority benefit of Taiwan application serial no. 88110184, filed Jun. 17,1999.
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for forming an epitaxial silicon-germanium (SiGe) layer.
2. Description of the Related Art
There is a continuing effort in the semiconductor industry to increase the integration on a semiconductor device. There have been, however, many problems in developing a highly integrated device due to physically imposed limitations of the semiconductor device itself. For example, in order to achieve a highly integrated device, there should be a reduction in the device dimension. A reduction of the dimension for a device, for example, a metal-oxide-semiconductor field effect transistor (MOSFET), parasitic capacitance and resistances at the gate and the source/drain region would increase correspondingly. Any reduction in the dimension, therefore, would inhibit the increase of the overall efficiency and performance of an integrated device. If the device were one step further being reduced in size, a majority area of the device would be occupied by the ohmic contact of the source/drain region. This problem is especially significant in a p-MOSFET device.
The charge carriers for a p-MOSFET device are mainly the electric holes. The mobility of the electric holes is worst than that of the electrons, which are the charge carriers for an n-MOSFET device. Therefore, when the device dimension is being reduced and the resistance is correspondingly increased, the adverse effects are more significant on a p-MOSFET device. As a result, the semiconductor industry has been focused on resolving the problem of reducing the dimension of a p-MOSFET device while maintaining or even increasing the device efficiency.
In recent years, growing a layer of silicon-germanium alloy (SiGe/Si) on a silicon wafer surface of a MOSFET device at a temperature below 600 degree Celsius using ultra high vacuum chemical vapor deposition (UHVCVD) or molecular beam epitaxy (MBE) has been developed. Since the radius of a germanium atom is greater than the radius of a silicon atom, when a portion of the silicon atoms in the silicon lattice is replaced by the germanium atoms, the entire lattice would be strained. As a result, even when the charge carrier densities are the same, the mobility of the electric holes and the mobility of the electrons for a strained silicon (Si) lattice or a strained SiGe/Si alloy lattice would increase 5 times and 10 times, respectively, when compared to the unstrained single silicon crystal.
Applying the SiGe/Si alloy formed according to the above method to form an integrated device seems to be able to resolve the problems encountered when the device dimension is being reduced. However, in order to integrate the entire manufacturing process and, at the same time, to avoid the lattice defect formation in the strained SiGe/Si alloy is not an easy task. Since, during the subsequent thermal processing, the high temperature would increase the vibrational motion of the atoms in the SiGe/Si alloy, the strained energy of the SiGe lattice is increased. When the strained energy of the lattice is reached to a certain degree, the excessive strained energy is released by breaking the bonding between atoms. The problem of a current leakage is thereby subsequently resulted.
The first problem encountered in applying a SiGe/Si alloy to manufacture a MOSFET device is the thermal oxidation process used in forming the gate oxide layer. The high temperature would induce defects in the SiGe lattice, directly affecting the quality of the gate oxide layer. Furthermore, the source/drain region of a MOSFET device in general has the ohmic contact, which is formed by the implanting and the driving-in of ions by means of an anneal process to form the source/drain region of the MOSFET device, followed by forming a conductive contact plug on the source/drain region. The high temperature in the anneal process, however, would destroy the lattice structure of the SiGe/Si alloy, resulting with defects in the lattice structure. A Schottky junction, on the other hand, can be formed by directly forming the metal plug on a predetermined region on the p-type or the n-type substrate. In this case, the high temperature anneal process is being avoided because the ion implantation process is not required. The source/drain region of a SiGe/Si alloy MOSFET, therefore, can not have the usual ohmic contact, but rather a Schottky junction is formed, and the Schottky junction is usually formed in high-speed circuitry. K. Ismail in the 1997 IEEE International Solid State Circuits Conference (paper FA7.1) indicates that the application of the Schottky junction is limited to lower integration devices, wherein the electrical consumption is low and the operational speed is fast. The application of the Schottky junction is therefore very limited.
Based on the foregoing, the present invention provides a method for growing an epitaxial silicon-germanium (SiGe) layer. This method includes conducting a cleaning process on the silicon substrate surface to remove the native oxide layer, followed by using a 40% to 60% concentrated hydrogen fluoride (HF) solution to vapor treat the silicon substrate surface and to suppress the native oxide formation. A germanium layer is the formed on the silicon substrate by physical vapor deposition. A rapid thermal annealing is then conducted at a temperature of about 850 degree Celsius to about 950 degree Celsius under an inert gas to form a SiGe/Si alloy on the substrate surface.
The present invention provides a method for growing an epitaxial SiGe layer and an oxide layer, the method includes removing the native oxide layer followed by performing a surface treatment process to suppress a native oxide formation on the substrate surface. The surface treatment process includes performing a hydrogen fluroide (HF) vapor treatment on the silicon substrate using a 40%-60% concentrated HF solution. After this, a layer of germanium is formed on the silicon substrate by physical vapor deposition. A rapid thermal anneal process is then conducted at a temperature of 850 degree Celsius to 950 degree Celsius under an inert gas to form a layer of SiGe/Si alloy. Thermal oxidation is further conducted to form a SiGe oxide layer on the SiGe/Si alloy.
The present invention provides a fabrication method for a Metal Oxide Semiconductor (MOS) device using an epitaxial SiGe layer. This method includes using a corrosive chemical to remove the native oxide layer on the silicon substrate surface, followed by using a 40% to 60% concentrated HF solution to vapor treat the silicon substrate surface. Physical vapor deposition is then conducted to form a germanium layer on the silicon substrate, followed by performing a rapid thermal anneal process at a temperature of about 850 to 950 degree Celsius under an inert gas to form a SiGe/Si alloy layer on the surface of the silicon substrate. Thereafter, thermal oxidation is conducted at about 850 degree Celsius to about 950 degree Celsius to form a SiGe oxide layer on the surface of the SiGe/Si alloy layer. The SiGe oxide layer on the surface of the SiGe/Si alloy layer thus serves as the gate oxide layer for the MOS device. Thereafter, a gate is formed on a predetermined region of the SiGe oxide layer. Ion implantation and annealing are further conducted to form a source/drain region on both sides of the gate.
According to the fabrication method of the present invention, the SiGe/Si alloy layer is formed under a high temperature, the lattice strained energy of the SiGe/Si alloy layer is going to be lower than the SiGe/Si alloy layer formed under a low temperature. The SiGe/Si alloy layer, formed according to the present invention, thereby can withstand the high temperature of the subsequent thermal processes of the semiconductor manufacturing, for example, the thermal oxidation process in forming the SiGe oxide layer or the anneal process after the implanting of ions for the source/drain region.